(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of avoiding the shadowing effect of the deposited copper seed layer that is deposited in a high aspect ratio opening.
(2) Description of the Prior Art
The conventional method of forming conducting lines and connecting vias within the construct of a semiconductor device is to deposit a layer of conducting material, such as aluminum, on the surface of a semiconductor using for instance a sputtering technique. Over this layer of conducting material is deposited a layer of photoresist, this photoresist is patterned and etched such that the conducting material that is to stay in place (to form the conducting lines or vias) is covered or protected by the photoresist. The unwanted conducting material is then removed, typically using anisotropic plasma etch. The openings created by the removal of the conducting material are filled with a dielectric material such as an oxide. The surface of the combined patterns of conductive material and dielectric can further be planarized by using a Chemical Mechanical Polishing (CMP) process that completes the creation of conducting lines or vias.
The continuous effort to improve semiconductor device performance brings with it a continuous effort of scaling down device feature sizes thereby improving the device performance speed and its functional capability. With the reduction in device feature sizes, the performance of the device becomes increasingly more dependent on the interconnections that are required between functional devices. In order to improve the interconnect aspect of semiconductor design and to reduce the relative impact of the device interconnects, integrated circuits are typically fabricated using multiple level interconnect schemes. Semiconductor devices are therefore often mounted on multi-chip modules such as polyimide substrates that contain buried wiring patterns to conduct electrical signals between various chips. The multiple layers of interconnect metalization contained within these multi-chip modules are typically separated by alternating layers of an isolating dielectric, the layers of dielectric serve as electrical isolation between the metal features. The metal that is used to construct the interconnect metal features is selected based on such performance characteristics as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing. For these reasons copper is often selected due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper does however suffer from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide causing severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. The emphasis on scaling down line width dimensions in Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (USLI) circuitry manufacturing has led to reliability problems including inadequate isolation, electromigration, and planarization. The damascene and dual damascene processes are important design approaches for VLSI/ULSI metal interconnect technologies. These approaches use metal to fill vias and interconnect lines followed by chemical mechanical polishing (CMP) with various Al, Cu and Cu-based alloys. A key problem is the filling of high aspect ratio vias in a homogeneous manner while creating the desired profile for the filling and at the same time avoiding seams or other surface irregularities. Several promising techniques have been explored to address this problem such as Metallo-Organic Chemical Vapor Deposition (MOCVD) and laser melting technology. Problems remain however with low deposition rates while the in-situ deposition of thin lines is very difficult. Furthermore, high temperature bias sputtering (i.e. above 450 degrees C.) technique has been attempted but this technique has limitations below 1 um geometries while such high temperatures lead to degrading the underlying metals. Conventional Chemical Vapor Deposition (CVD) technology or plating has not yet been applied to creating interconnect metal where high aspect ratio openings are applied. Existing Physical Vapor Deposition (PVD) techniques are at this time also not available to adequately address this problem.
It is therefore clear that, as the density of circuit components contained within a semiconductor die has increased and the circuit components have decreased in size and are spaced closer together, it has become increasingly difficult to access selectively a particular region of the silicon wafer through the various layers that are typically superimposed on the surface of the silicon wafer without undesired interference with other active regions.
It is especially important to have a technology that can etch openings that have essentially vertical walls, most notably when the openings are to extend deeply into the surface layers. Additionally, to tolerate some misalignment in the masks used to define such openings, it is advantageous to provide protection to regions that need isolation but that inadvertently lie partially in the path of the projected opening. To this end it is sometimes the practice to surround such regions with a layer of material that resists etching by the process being used to form the openings. Accordingly, a technology that provides the desired results will need an appropriate choice both in the materials used in the layers and the particular etching process used with the materials chosen.
Dry etching, such as plasma etching and reactive ion etching, has become the technology of choice in patterning various layers that are formed over a silicon wafer as it is processed to form therein high density integrated circuit devices. This is because it is a process that not only can be highly selective in the materials it etches, but also highly anisotropic. This makes possible etching with nearly vertical sidewalls.
Basically, in plasma etching as used in the manufacturing of silicon integrated devices, a silicon wafer on whose surface have been deposited various layers, is positioned on a first electrode in a chamber that also includes a second electrode spaced opposite the first. As a gaseous medium that consists of one or more gasses is flowed through the chamber, an r-f voltage, which may include components at different frequencies, is applied between the two electrodes to create a discharge that ionizes the gaseous medium and that forms a plasma that etches the wafer. By appropriate choice of the gasses of the gaseous medium and the parameters of the discharge, selective and anisotropic etching is achieved.
Recent requirements for the creation of holes within deep layers of either conducting or other materials have resulted in creating openings that have aspect ratios in excess of 3. It is beyond the capability of the existing techniques to fill gaps of this aspect ratio with High Density Plasma-oxide (HDP-oxide). This lack of adequate filling of gaps also occurs for holes that have a reentrant spacer profile. A reentrant spacer profile is a profile where the walls of the openings are not vertical but are sloped, this sloping of the walls makes complete penetration of the HPD-oxide into the hole difficult and, under certain conditions, incomplete.
In a typical process of semiconductor IC fabrication, a contact/via opening is etched through an insulating layer. The contact opening connects to an underlying conductive area to which electrical contact is to be established. A glue layer, typically titanium, is conformally deposited within the contact/via opening. Next, a titanium nitride barrier is formed within the contact/via opening. This barrier layer may be deposited by reactive sputtering or by CVD. With increased reduction in device feature size, the CVD method of forming a barrier layer becomes essential. CVD processes are preferred because they can provide conformal layers of any thickness. Thinner barrier layers are preferred because of the shrinking feature sizes. A layer of conducting material, typically tungsten, is deposited within the contact/via opening to form a plug filling the contact/via opening. A second conducting layer, such as an aluminum alloy, is deposited over the tungsten plug and patterned to complete the metalization. Using a typical etchback process to form the tungsten plug, the thin CVD titanium nitride barrier layer may be etched away, exposing the underlying titanium layer. During the subsequent scrub cleaning process, the exposed titanium underlayer will be oxidized. This will result in difficulty in etching the titanium oxide layer causing metal interconnect shorting due to the residues remaining after etching. A typical glue layer can contain titanium and has a thickness of between about 100 and 400 Angstrom. A typical glue barrier layer (CVD deposited) can contain titanium and has a typical thickness of between about 50 and 400 Angstrom.
The invention addresses a process for filling high aspect ratio openings with copper by first depositing a thin layer of pure copper (as a seed layer) on top of the barrier layer of TaN. The layer of pure copper acts as a plating conductive layer and a nucleation layer. The minimum thickness of the seed layer is about 50 Angstrom, this thickness is required to achieve a reliable gap fill. The problem that is encountered with the deposition of the seed layer in openings that have a high aspect ratio is that the seed layer will not be evenly deposited over the sidewalls of the opening. The high aspect ratio causes a shadowing effect whereby the deposition of the seed layer on the sidewalls of the opening varies from 50 to 80 Angstrom. Moreover, in a typical deposition of the pure copper seed layer, the pure copper readily oxidizes at room temperature forming CuO.sub.x. This CuO.sub.x must, during a typical creation of a copper via plug, be removed before copper plating with a Electrical Chemical Deposition (ECD) bath causing further problems of lack of repeatability in creating a uniform seed layer over the sidewall of the opening.
FIG. 1 shows a cross section of a copper plug created using Prior Art technology. A metal contact 11 is formed in a surface 10, typically the surface of a semiconductor substrate where the metal contact is part of a metal interconnect network that has been created in the surface of the substrate. Opening 18, in this case a dual damascene opening, has been created in the conventional manner in two layers of dielectric 12 and 14. A barrier layer (not highlighted for the sake of clarity) has been deposited over the sidewalls of the opening 18, a seed layer 16 of pure copper has been deposited over the barrier layer over the sidewalls of the opening 18. Area 20 is highlighted as an area where the pure copper of the seed layer 16 has oxidized and has been etched away by the ECD bath. The seed layer is, due to its oxidation, not thick enough and not uniform in molecular structure in area 20 and is etched through by the Electrical Chemical Deposition (ECD) bath. It is clear from FIG. 1b that the copper fill that is applied to opening 18 does not have the benefit of a seed layer in region 22 resulting in problems of plug reliability.
U.S. Pat. No. 5,112,448 (Chakravorty) shows a Cu plating process with a Cu seed layer in the trench.
U.S. Pat. No. 5,898,222 (Farooq et al.) teaches a Cu plating process with a seeding layer.
U.S. Pat. No. 5,462,897 (Baum et al.) teaches a method to electroplate Cu to form an interconnect by covering the seed layer with a dielectric layer.
U.S. Pat. No. 5,266,446 (Chang et al.), U.S. Pat. No. 5,436,504 (Chakravorty et al.) and U.S. Pat. No. 5,899,704 (Kwon) recite other Cu electroplating processes.